The present invention is related in general to the field of semiconductor device assembly and packaging, and more specifically to fabricating integrated circuit (IC) devices having three dimensional packaging.
It is well known that the consumers of the next generation electronic devices are demanding increased functions and features that are packed in a smaller size, consuming less power, and costing less than the earlier generation. Semiconductor device manufacturers are responding by incorporating improved three dimensional packaging technologies such as systems in package (SiP), Multi-Chip Packages (MCPs), Package-on-Package (PoP), and similar others that provide vertical stacking of one or more dies and/or packages that are integrated to operate as one semiconductor device. For example, PoP packages are commonly used in products desiring efficient access to memory while reducing size, such as cellular telephones.
PoP typically includes at least one die such as a logic chip in a bottom package. A top surface of the substrate is used as a receptor to mount a top package such as a memory chip. The top package is electrically coupled to the bottom substrate by ball grid arrays (BGAs) or similar other. If there is more than one die in the bottom package, then a cavity substrate is desirable as it allows for a smaller mold cap that does not interfere with the top package. The cavity substrate may be fabricated as a monolith substrate or as multiple substrates attached together to form a center cavity. Formation of the center cavity in a monolithic substrate is typically costly and complex, whereas formation of the center cavity using multiple substrates is more cost effective. However, during an assembly of a PoP package, encapsulation of the die by a molding compound often results in the molding compound flowing between the multiple substrates in an unpredictable and uneven manner, thereby potentially inducing uneven stress.